Network processing at multi-gigabit data rates, for example at oc-192 or higher data rates, requires multiple multi-threaded processors. The number of processors in a multi-processor system is limited by current integrated circuit technology. Network processing at multi-gigabit data rates requires packet buffering to be done internal to the network processor. The amount of embedded memory is also limited by current integrated circuit technology. In order to properly process multiple packets in a multi-processor system, strict packet ordering between the incoming and outgoing packet path must be maintained. The problem is to maximize the number of processors and minimize the number of packet buffers required while ensuring strict packet order.
A number of approaches to this problem have been attempted in the art. One approach involves removing packets from the processors in the order of completion. The packets are buffered until processing of the earlier packets is completed. This approach suffers from a number of drawbacks, which include increased internal memory requirements, increased routing resource requirements, and additional operations to move data.
A second approach known in the art involves allowing packets to remain in processor memory until processing of the earlier packets is completed. This approach also suffers from a number of drawbacks which include increased internal memory requirements, increased packet routing resource requirements, and the problem of processor stalling and/or thread stalling while waiting for the earlier packets to be processed.
Accordingly, there remains a need for a solution, which addresses the shortcomings and improves on the known approaches.